Welcome！[Sign In] ！[Sign Up]！
Front-page it | Collect it | [中国-简体中文]
FAQ Fav
Location:
Search - clock verilog

Search list

[Embeded-SCM Develop] verilog-clock

Description: 用verilog编写的多功能数字钟--Multifunctional digital clock written in verilog.
Platform: | Size: 1024 | Author: 李瑞 | Hits:

[VHDL-FPGA-Verilog] Verilog DHL数字钟

Description: 用Verilog DHL语言编写的一个数字钟程序,除了基本计数,还具有校时,闹钟功能-Verilog language used in the preparation of a digital clock procedures, in addition to the basic count, but also with school, an alarm clock
Platform: | Size: 2048 | Author: 谢树扬 | Hits:

[VHDL-FPGA-Verilog] time_clock

Description: 实用闹钟的verilog代码。不是vhdl的！经过ldv验证-practical alarm the Verilog code. VHDL is not! After certification ldv
Platform: | Size: 4096 | Author: 徐哦俄 | Hits:

[VHDL-FPGA-Verilog] clockv

Description: 使用Verilog语言编写的数字钟程序.有慢校时,快校时,闹钟等功能.-use Verilog language prepared by the digital clock procedures. Schools are slow, quick school, alarm clock functions.
Platform: | Size: 5120 | Author: 刘吉 | Hits:

[VHDL-FPGA-Verilog] shzzh

Description: 这是在FPGA上实现的数字钟功能，用VERILOG语言编程，已功过编译，仿真验证-This is the FPGA to achieve the digital clock function with verilog programming language, compiler has merits and demerits. Simulation
Platform: | Size: 63488 | Author: 吴乔红 | Hits:

[MPI] clock

Description: 用Verilog HDL写的数字时钟,已经在开发板上验证过的,绝对原创,使用数码管进行显示!-Written using Verilog HDL Digital Clock, has been verified in the development of on-board absolute originality, the use of digital tube display!
Platform: | Size: 2048 | Author: 吴俊泉 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 完整的VerilogHDL时钟例程，已通过硬件仿真。-VerilogHDL complete clock routines, has passed through hardware emulation.
Platform: | Size: 28672 | Author: xuping | Hits:

[VHDL-FPGA-Verilog] VerilogHDL_clock

Description: 基于Verilog HDL设计的多功能数字钟，有兴趣的-Verilog HDL-based design of multi-function digital clock, interested
Platform: | Size: 38912 | Author: 沈三思 | Hits:

[Home Personal application] digtalclk

Description: 用Altera公司的QuartusII编写的电子钟程序，可以下载至开发板，实现一个智能数字钟功能，计时，校时，闹钟，跑表等功能，也可用于学习verilog HDL语言与数字逻辑-Using Altera s QuartusII procedures for the preparation of electronic bell, you can download to a development board, the realization of an intelligent digital clock function, time, school time, alarm clock, stopwatch functions can also be used to study verilog HDL language and digital logic
Platform: | Size: 2094080 | Author: 张欢 | Hits:

[VHDL-FPGA-Verilog] digital_clock

Description: 用veriolg写的数字钟实验，具有定点报时，闰年判断，年月日显示，下载平台为spantan3s400。有详细注解。适合verilog学习-Written by veriolg digital clock experiments with fixed time, to determine leap year, date display, download platform spantan3s400. Have a detailed annotation. Suitable for learning Verilog
Platform: | Size: 1186816 | Author: 屠宁杰 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 自己编写的一个verilog时钟程序，在xilinx的ISE仿真通过-I have written a Verilog clock procedures, in Xilinx s ISE simulation through
Platform: | Size: 327680 | Author: lg | Hits:

[Program doc] clock

Description: verilog编写的时钟控制程序，在xilinx芯片上开发。具有案件防抖等考虑，-Verilog clock control procedures to prepare, in the Xilinx chip development. Anti-shake, such as with the case considered
Platform: | Size: 10240 | Author: 王忠 | Hits:

[VHDL-FPGA-Verilog] clock

Description: dp_xiliux 的 CPLD Verilog设计实验,时钟演示.代码测试通过. -dp_xiliux the CPLD Verilog design experiments, clock demo. code test.
Platform: | Size: 79872 | Author: pp | Hits:

[SCM] Verilog(clock)

Description: 用VERILOG语言编写的电子钟程序.是用GW48教学实验箱仿真-Verilog language using an electronic bell procedures. GW48 is teaching me the experimental simulation
Platform: | Size: 7168 | Author: 阿洪 | Hits:

[VHDL-FPGA-Verilog] Clock

Description: 用Verilog 实现的电子时钟，给初学者一个模版，学习Verilog。-Using Verilog realize an electronic clock, a template for beginners to learn Verilog.
Platform: | Size: 11264 | Author: Jason | Hits:

[VHDL-FPGA-Verilog] clock

Description: 本实验实现一个能显示小时，分钟，秒的数字时钟（贝一特电子）Verilog源码-The experimental realization of a can show hours, minutes, seconds, digital clock (a special e-bay) Verilog source
Platform: | Size: 1024 | Author: 黄建 | Hits:

[VHDL-FPGA-Verilog] verilog

Description: 多功能数字时钟的verilog语言描述，基于quarters II平台-Multifunction digital clock verilog language description of quarters II-based platforms
Platform: | Size: 7168 | Author: lvlv | Hits:

[VHDL-FPGA-Verilog] clock

Description: 采用Verilog HDL语言编写的多功能数字钟，包括四个功能：时间显示与设置、秒表、闹钟、日期显示与设置.-Using Verilog HDL language multi-functional digital clock, including the four functions: time display and settings, stopwatch, alarm clock, date display and settings.
Platform: | Size: 3100672 | Author: 陈涵 | Hits:

[VHDL-FPGA-Verilog] clock

Description: 多功能数字钟Verilog HDL的源码，能够整点报时，报整点数，设定任意时刻闹钟，低音高音两种频率。-Multi-function digital clock Verilog HDL source code, set the alarm clock at any time, bass treble two frequencies. It s for FPGA.
Platform: | Size: 984064 | Author: Stone Lei | Hits:

[VHDL-FPGA-Verilog] clock

Description: verilog数字钟 Verilog HDL 写的不是很好,有好的就不要下我的了-verilog clock
Platform: | Size: 1024 | Author: Tuyan | Hits:
« 12 3 4 5 6 7 8 9 10 ... 31 »

CodeBus www.codebus.net